Caches are designed to alleviate this bottleneck by making the data used most often by the CPU instantly available.
Some MPS Pentium systems, and all MPS Pentium Pro and Pentium II systems, have independent L2 caches.
We then looked at the Arp caches of the problem servers and compared them to each other.
A set associative cache memory nothing more than several direct-mapped caches operated in parallel.
This is a strange twist on the usual case where the squid caches are located at the client's network.