A simple parity checking error control method used in asynchronous transmission and primary storage. See Table V-2.VRC entails the appending of a parity bit at the end of each character or value to create an odd or even total mathematical bit value.The letter V, for example, in ASCII, is coded as a bit sequence of 0110101, which is an even number of marks, or 1 bits. If the network is set for the default odd parity, the parity bit would be a 1, as that would create an eight-bit byte with the sequence 01101011, thereby creating an odd parity value. Alternatively, the parity bit would be a 0 if the network is set for even parity, as that would create an eight-bit byte with the sequence 01101010, thereby retaining an even parity value. The receiving device executes the same mathematical process to verify that the correct total bit value was received, hence the use of the terms redundancy and checking. Speaking in terms of the logical manner in which humans add numbers physically positioned in columns, the two devices sum the bit values vertically, as represented in the following table, hence the use of the term vertical.VRC is easily and inexpensively implemented in computers employing asynchronous transmission, but is highly unreliable, as two errored bits in a character yield an undetectable error. Further, VRC provides no inherent means of error correction.VRC often is characterized as send and pray.

Table V-2: Vertical Redundancy Check (VRC)

Bit/Value	C	O	N	T	R	O	L
1	1	1	0	0	0	1	0
2	1	1	1	0	1	1	0
3	0	1	1	1	0	1	1
4	0	1	1	0	0	1	1
5	0	0	0	1	1	0	0
6	0	0	0	0	0	0	0
7	1	1	1	1	1	1	1
8 (Odd Parity)	0	0	1	0	0	0	0

See also asynchronous, error control, LRC, parity bit, and parity check.