The most common ASIC development technology. Each standard cell vendor has its own library of circuits that range from primitive logic gates to more complex functions such as memory blocks and microprocessor cores. Based on the customer's design, the required circuits are placed on the chip and connected using "place-and-route" software. Unlike gate arrays, which are partially fabricated chips with repetitive blocks of unconnected transistors, standard cell designs are created on blank wafers. They are more efficient and use less silicon real estate than gate arrays. See gate array and ASIC.