# parity checking - Computer Definition

An error detection technique that tests the integrity of digital data in the computer. Parity checking adds an extra parity cell to each 8-bit byte of memory, thus creating a nine-bit structure.
In an "even parity" system, a 0 is stored in the parity bit if there is an even number of bits in the byte; if an odd number, a 1 is stored to make the total number of bits even. In "odd parity" systems, the opposite occurs; a 0 parity bit if odd, a 1 parity bit if even to make the total number odd.
**Only Good for One-Bit Errors**
Each time a byte is transferred, the parity bit is checked. One-bit parity systems will detect if one of the eight bits in the byte has been erroneously switched from 1 to 0 or from 0 to 1. However, it cannot detect a two-bit error, because if two bits in the byte are reversed, the even or odd number remains the same. Error-correcting code (ECC) is a more robust memory checking system (see ECC memory).
**Plenty of "NO" Parity Around**
There are 12% more memory cells in 9-bit parity chips than there are in 8-bit memory. To shave costs, many computers are built with non-parity memory, and it is truly a miracle that the billions of non-parity computers work as well as they do. See RAID, ECC memory and soft error.