A process technology that reduces the size of the chip without redesigning the circuits to fit into the smaller area. Normally, when shrinking a chip to a smaller die size, some of the circuit design has to be reworked. The half-node is different; the design remains the same, and only the real estate has been shrunk. For example, in 2008, Altera introduced an FPGA with a 40 nm half-node: 5 nm less than the standard 45 nm. This 11% reduction in size reduces power consumption. See process technology.