A type of ASIC chip that is partially finished with rows of the transistors and resistors built in but unconnected. The chip is completed by designing and adhering the top metal layers that provide the interconnecting pathways. These final masking stages are less costly than designing a full custom chip from scratch, which requires a new photo-mask for every transistor and interconnection layer.

The gate array is made up of "basic cells," each cell containing some number of transistors and resistors depending on the vendor. Using a cell library (gates, registers, etc.) and a macro library (more complex functions), the customer designs the chip, and the vendor's software generates the interconnection masks. Some cells go wasted on gate array designs, which is the penalty for having fixed locations for everything. See PLD, ASIC, hard macro and soft macro.